Cache Access Counter enable and clear register
L1_IBUS0_CNT_ENA | The bit is used to enable ibus0 counter in L1-ICache0. |
L1_IBUS1_CNT_ENA | The bit is used to enable ibus1 counter in L1-ICache1. |
L1_IBUS2_CNT_ENA | Reserved |
L1_IBUS3_CNT_ENA | Reserved |
L1_BUS0_CNT_ENA | The bit is used to enable dbus0 counter in L1-DCache. |
L1_BUS1_CNT_ENA | The bit is used to enable dbus1 counter in L1-DCache. |
L1_DBUS2_CNT_ENA | Reserved |
L1_DBUS3_CNT_ENA | Reserved |
L1_IBUS0_CNT_CLR | The bit is used to clear ibus0 counter in L1-ICache0. |
L1_IBUS1_CNT_CLR | The bit is used to clear ibus1 counter in L1-ICache1. |
L1_IBUS2_CNT_CLR | Reserved |
L1_IBUS3_CNT_CLR | Reserved |
L1_BUS0_CNT_CLR | The bit is used to clear dbus0 counter in L1-DCache. |
L1_BUS1_CNT_CLR | The bit is used to clear dbus1 counter in L1-DCache. |
L1_DBUS2_CNT_CLR | Reserved |
L1_DBUS3_CNT_CLR | Reserved |